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jrn rajasthan vidyapeeth university b tech |
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Re: jrn rajasthan vidyapeeth university b tech
Janardan Rai Nagar Rajasthan Vidyapeeth University is a deemed university in the city of Udaipur in the Indian state of Rajasthan. It got the status of deemed university in 1987. the Syllabus of the : DIGITAL ELECTRONICS Subject of the B.tech Aeronautical Engineering is given below DIGITAL ELECTRONICS NUMBER SYSTEMS AND CODES: Binary Number System, Octal Number System, Hexadecimal Number System, Bits and Bytes , 1’s and 2’s Complements, Decimal –to- Binary Conversion, Decimal-to- Octal Conversion, Decimal –to-Hexadecimal Conversion, Binary –octal and Octal – Binary Conversions , Hexadecimal – Binary and Binary –Hexadecimal Conversion, Hexadecimal –Octal and Octal –Hexadecimal Conversion. BCD Code, Excess -3 Code , Gray code , Alphanumeric Codes ,Parity Bits, Hamming Code, Floating Point Numbers. 2. BINARY ARITHNETIC Basic Rules of Binary , Addition of Larger Bit Binary Numbers, Subtraction of Larger Bit Binary Numbers, Addition Using 2’s Complement Method, Subtraction Using 2’s Complement Method, Binary Multiplicity –repeated Left Shift and Add Algorithm , Binary Divison – Repeated Right Shift and Subtract Alogrithm. 3. LOGIC GATES AND LOGIC FAMILIES: Positive and Negative Logic, Truth Tables, Logic Gates, Fan out of Logic Gates, Logic Families, TTL Logic Family, CMOS Logic Family, ECL Logic Family,NMOS AND PMOS Logic Families. 4. BOOLEN ALGEBRA AND MINIMISATION TECHNIQUES: Boolean Algebra vs. Ordinary Algebra , Boolean Expressions- Variables and Literals, Boolean Expressions – Equivalent and Complement,Theorems of Boolem Algebra, Minimisation Techniques ,Sum –of – products Boolen Expressions, Quine- Mccluskey Tabular Method, Karnaugh Map Method,Karnaught Maps for Boolean Expressions : With More Than Four Variables. 5. COMBINATIONAL LOGIC CIRCUITS: Combinational Circuits, Implementating Combinational Logic, Arithmetic Circuits –Basic Building Blocks, Adder- Subtractor, BCD Adder, Carry Propagation- Look Ahead Carry Generator, Arithmetic Logic Unit (ALU), Mulitpliers, Magnitude Comparator, Parity Generator and Checker, De- multiplexers and Decoders, Encoders, Read Only Memory (ROM), Programmable Logic Array (PLA) 6. FLIP FLOPS AND RELATED DEVICES: R-S Flip Flop , Level Triggered and Edge Triggered Flip Flops, J.K Flip Flop, Master-slave Flip Flops, T-flip Flop, D-flip Flop, Synchronous and Asynchronous Inputs. 7. COUNTERS AND REGISTERS: Ripple Counter vs. Synchronous Counter, Modulus (or Mod-Number)of a Counter, Propogation Delay in Ripple Counters, Binary Ripple Counters- Operational Principle, Binary Ripple Counters with Modulus Less Than (2 ),Synchronous (or Parallel ) Counters, Up/Down Counters, Decade and BCD Counters , Presettable Counters, Shift Register, Serial-in Serial –out Shift Register, Serial –in Parallel-out Shift Register, Parallel – in ,Serial –out Shift Register, Parallel-in , Parallel –out Shift Register, Shift Register Counters- Ring Counter, Shift Counter. For any Query you may Contact to the Janardan Rai Nagar Rajasthan Vidyapeeth University the contact details Are given below Contact Details : Janardan Rai Nagar Rajasthan Vidyapeeth University Address: Pratap Nagar, Udaipur, Rajasthan 313001 Phone: 0294 249 3493 |
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