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Sathyabama Institute of Science and Technology M.Tech - VLSI SECA5201 Mixed Signal Integrated Circuit Design Syllabus

SATHYABAMA INSTITUTE OF SCIENCE AND TECHNOLOGY SCHOOL OF ELECTRICAL AND ELECTRONICS ENGINEERING

SECA5201
MIXED SIGNAL INTEGRATED CIRCUIT DESIGN
(For VLSI)
L T P Credits Total Marks
3 0 0 3 100

UNIT 1 CURRENT MIRRORS 9 Hrs.
Analog Octagon - Simple CMOS current mirror - source degenerated current mirrors - high output impedance current mirrors
- Bipolar current mirrors - Advanced current mirrors : Cascode stage Wilson current mirror - Bipolar current mirrors - Bipolar
gain stages - Widlar current mirror - folded cascade and current mirror op amp - Mixed Cell Layout.

UNIT 2 OPERATIONAL AMPLIFIER DESIGN 9 Hrs.
Performance Parameters - All NMOS enhancement mode Operational Amplifier Design - Two stage CMOS op amp - Gain
Boosting - op amp as a comparator - Charge injection errors - Linear settling time revisited, fully differential op amp -
Stability and Frequency Compensation - Phase margin - Latched Comparators - Basics of OTA Amplifiers Design.

UNIT 3 SWITCHED CAPACITOR CIRCUITS 9 Hrs.
Basic SC circuits: Parallel - Series – Series - Parallel - Bilinear Operation and Analysis - Switched capacitor amplifier -
Switched capacitor integrators - SC Trans resistance circuits - Z Domain Model Representation of Switched Capacitor
Circuits - Switched Capacitor filter Design - First order and Second order.

UNIT 4 DATA ACQUISITION SYSTEMS 9 Hrs.
Basics of Sample and hold circuits - CMOS S/H circuits - Bipolar and BiCMOS S/H circuits - translinear gain cell -
Translinear multiplier - Band gap reference basics: Supply Independent Biasing, Temperature Independent References,
PTAT Current Generation - High speed A/D and D/A converters - High resolution converters - Sigma delta A/D converter -
Interpolative Modulators - Testing of converters.

UNIT 5 PLL AND NEURAL INFORMATION PROCESSING 9 Hrs.
Voltage Controlled Oscillators - Mathematical Model of VCO - Phase - Locked Loops: Basic PLL Topology - Phase Detector-
Loop Filter - Charge Pump PLL - Linearized PLL - Nonideal Effects in PLLs - Jitter in PLLs - Frequency Synthesizer -
Biologically Inspired Neural Networks - ANN Models - Genetic algorithm - Low Power Neural Networks.
Max.45 Hrs.

COURSE OUTCOMES
On completion of the course, student will be able to
CO1 - Design and implementation of current mirrors.
CO2 - Design and analysis of operational amplifier.
CO3 - Comprehensive understanding of Switched Capacitor circuits.
CO4 - Study of data acquisition systems.
CO5 - Understanding of phase locked loops and neural processing.
CO6 - Design, principles, operation and analysis of mixed signal circuits.

TEXT / REFERENCE BOOKS
1. Behzad Razavi “Design of Analog CMOS Integrated Circuits”, Tata McGraw Hill India Pvt. Ltd., 2008.
2. David A Johns and Ken Martin “Analog Integrated Circuit Design”, John Wiley & Sons, 2004.
3. Allen Holberg, "CMOS Analog Circuit Design", Oxford Publications, 2002.
4. Franco Maloberti, “Analog Design for CMOS VLSI Systems”, Kluwer Academic Publisher, 2001.
5. Roger T.Howe and Charles G.Sodini, “Micro Electronics an Integrated Approach”, Pearson Education Pvt. Ltd., 2004.
6. Baker, Li, Boyce, "CMOS Mixed Circuit Design", Wiley Publications, 2002.
7. Roubik Gregorian “Analog MOS Integrated Circuits for Signal Processing”, John Wiley and Sons, 2004.
8. Rudy Van de Plassche “CMOS Integrated A/D and D/A converters”, Kluwer Academic Publisher, 2003.

END SEMESTER EXAMINATION QUESTION PAPER PATTERN
Max. Marks: 100 Exam Duration: 3 Hrs.
PART A: 5 Questions of 6 Marks each – No choice 30 Marks
PART B: 2 Questions from each unit of internal choice, each carrying 14 Marks 70 Marks