| February 7th, 2013 11:26 AM | |
| vikash | Re: IOE Entrance Com Here I am providing some of the questions of IOE : Why the Eber-Moll model is called âTâ model? Describe charge distribution in the base. 2. What are the parameters to characterize digital ICs, how can you compare performance of it. 3. Write operation procedures for monostable multivibrator when it is in stable state. 4. Calculate maximum low input voltage for DTL circuit, when supply voltage is 5 volts and take the appropriate values of resisters. 5. Explain the operation of DTL logic circuit. 6. Explain the operation of TTL logic circuit when all inputs high. 7. Write down the three formulae used in n-channel MOSFET. 8. What are the basic properties of logic gates? Write down, MOSFET inverters with resistive load. 9. Justify all possible cases for voltage input and output characteristics for NMOS inverter with depletion load. 10. What are the differences in the concept of effective width to length ratios of NMOS logic circuit? 11. Analyze the CMOS inverter for VI = VDD when both transistors are enhancement mode devices. 12. Give the possible logics for CMOS inverter design consideration. 13. Write FAN-IN and FAN-OUT of CMOS inverter. 14. Write operation procedures for SRAM. 15. Realize the PLA and make PLA tables for the following logic expressions: F0 = ∑m (0, 8, 15, 12, 5, 7, 3) F1 = ∑m (2, 5, 6, 8, 10, 13, 15) F3 = ∑m (1, 4, 5, 7, 9, 12, 15) F4 = ∑m (5, 6, 8, 10, 11) 16. What are the main steps follow during IC fabrication? 17. Write short notes. a. Noise Margin b. Charge Coupled Devices c. Power dissipation in CMOS inverter d. NMOS transmission gate e. Comparison between BJT and MOS If you want to get the more questions , please download the file . |
| February 1st, 2013 03:17 PM | |
| babu.thiruvengedam | IOE Entrance Com Hi, I want to get admission in the IOE, Please give me the sample paper ? |
