| March 20th, 2021 12:00 PM | |
| ReenaK | Sathyabama Institute of Science and Technology M.E. - Applied Electronics SECA7015 Advanced ASIC Design Syllabus Sathyabama Institute of Science and Technology M.E. - Applied Electronics SECA7015 Advanced ASIC Design Syllabus SATHYABAMA INSTITUTE OF SCIENCE AND TECHNOLOGY SCHOOL OF ELECTRICAL AND ELECTRONICS ENGINEERING SECA7015 ADVANCED ASIC DESIGN (For VLSI & AE) L T P Credits Total Marks 3 0 0 3 100 UNIT 1 INTRODUCTION TO ASICS, CMOS LOGIC AND ASIC LIBRARY DESIGN 9 Hrs. Types of ASICs - Design Flow - CMOS transistors, CMOS design rules - Combinational Logic Cell – Sequential logic cell - Data path logic cell - transistors as resistors - transistor parasitic capacitance - Logical effort - Library cell design - Library architecture. UNIT 2 PROGRAMMABLE LOGIC CELLS AND I/O CELLS 9 Hrs. Anti fuse – static RAM – EPROM and EEPROM technology – PREP bench marks – Actel ACT – Xilinx LCA– Altera FLEX – Altera MAX DC & AC inputs and outputs – Clock and power inputs – Xilinx I/O blocks-Actel ACT – Xilinx LCA – Xilinx EPLD – Altera MAX 5000 and 7000 – Altera MAX 9000 Altera FLEX. UNIT 3 FLOOR PLANNING, PLACEMENT AND ROUTING 9 Hrs. System partition - FPGA partitioning - partitioning methods - floor planning - placement - physical design flow - global routing - detailed routing - special routing - circuit extraction - DRC. UNIT 4 SOC FUNDAMENTALS, SOFTWARE AND ENERGY MANAGEMENT 9 Hrs. Essential issues of SoC design – A SoC for Digital still camera – multimedia IP development: Image and video Codecs. SoC embedded software – energy management techniques for SoC design. UNIT 5 NOC DESIGN 9 Hrs. Practical Design of NoC, NoC Topology-Analysis Methodology, Energy Exploration, NoC Protocol Design, Low-Power Design for NoC: Low-Power Signaling, On-Chip Serialization, Low-Power Clocking, Low-Power Channel Coding, Low-Power Switch, Low-Power Network on Chip Protocol. Max. 45 Hrs. COURSE OUTCOMES On completion of the course, student will be able to CO1 - Understand the CMOS design rules CO2 - Analyse the logic cells of combinational, sequential and datapath. CO3 - Apply the programming technique in logic and I/O cells. CO4 - Describe the methods for partitioning, floor planning and routing. CO5 - Evaluate the SoC for Digital Still Camera. CO6 - Design the low-power NoC. TEXT / REFERENCE BOOKS 1. M.J.S. Smith, “Application Specific Integrated Circuits”, Addison Wesley Longman Inc., 1997. 2. Youn-Long, Steve Lin, “Essential Issues of SoC Design: Designing Complex Systems- On- Chip”, Springer, 2006. 3. Wolf Wayne, “FPGA Based System Design”, Pearson Education India, 2004. 4. Axel Jantsch, Hannu Tenhunen, “Network on chips”, Kluwer Academic Publishers, 2003. 5. Hoi-junyoo, Kangmin Lee, Jun Kyoung Kim, “Low power NoC for high performance SoC design”, CRC Press, 2008. 6. Vijay K. Madisetti, Chonlameth Arpikanondt, “A Platform-Centric Approach to System- on- Chip (SOC) Design”, Springer, 2005. END SEMESTER EXAMINATION QUESTION PAPER PATTERN Max. Marks: 100 Exam Duration: 3 Hrs. PART A: 5 Questions of 6 marks each - No choice 30 Marks PART B: 2 Questions from each unit of internal choice, each carrying 14 marks 70 Marks |
