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Sathyabama Institute of Science and Technology B.E. - Electronics and Communication Engineering Part Time SECA3006 ASIC Design Syllabus

SATHYABAMA INSTITUTE OF SCIENCE AND TECHNOLOGY SCHOOL OF BUILDING AND ENVIRONMENT

SECA3006 ASIC DESIGN
L T P Credits Total Marks
3 0 0 3 100

UNIT 1 TYPES OF ASIC AND BASICS OF CMOS LOGIC DESIGN 9 Hrs.
Types of ASICs – Design Flow – CMOS transistors, CMOS design rules – Combinational Logic Cell – Sequential logic cell –
Data path Logic cell – transistors as resistors – transistor parasitic capacitance – Logical effort.

UNIT 2 PROGRAMMABLE ASIC, LOGIC CELL AND I/O CELL 9 Hrs.
Antifuse- static RAM-EPROM and EEPROM technology-PREP bench marks –Actel ACT – Xilinx LCA –Altera FLEX- Altera
MAX DC & AC inputs and outputs – Clock and power inputs – Xilinx I/O blocks – Xilinx LCX – Xilinx EPLD –Altera MAX
9000, Altera FLEX.

UNIT 3 ASIC DESIGN FLOW 9 Hrs.
System partition-FPGA partitioning-partitioning methods-floor planning-placement-physical design flow-global routing
detailed routing-special routing-circuit extraction-DRC.

UNIT 4 SOC DESIGN 9 Hrs.
Essential issues of SoC design- A SoC for Digital Still Camera – multimedia IP development –-Basic concepts of Bus based
Communication Architectures. SoC embedded software- energy management techniques for SoC design.

UNIT 5 NOC DESIGN 9 Hrs.
Practical Design of NoC, NoC Topology-Analysis Methodology, Energy Exploration, NoC Protocol design, Low Power
Design for NoC, - Low Power Clocking, Low Power Channel Coding,- Low Power Switch, Low Power Network on Chip
Protocol.
Max. 45 Hrs.

COURSE OUTCOMES
On completion of the course, student will be able to
CO1 - Enumerate the various types of ASICs, the CMOS logic design.
CO2 - Illustrate the programmable logic cells and I/O cells.
CO3 - Demonstrate the practical design steps of Backend VLSI design.
CO4 - Describe the fundamentals of SoC design and Software with energy Management.
CO5 - Explain Practical design steps of NoC and Methodology.
CO6 - Implement Low Power NoC design.

TEXT / REFERENCE BOOKS
1. M.J.S.Smith, “Application Specific Integrated Circuits”, Pearson Edition, 2002.
2. Youn-Long, Steve Lin, “Essential Issues of SoC Design, Designing Complex Systems On Chip", Springer, 2010.
3. Wolf Wayne, “FPGA Based System Design”, Pearson Education, India 2004.
4. Axel Jantsch, Hannu Tenhunen, “Network on Chips”, Kliwer Academic Publishers, 2003.
5. Hoi-jun yoo,Kangmin Lee, Jun Kyoung Kim, “Low Power NoC for high performance Soc design” CRC press, 2008.
6. Vijay K.Madisetti Chonlameth Arpikanodt, “A Platform-Centric Approach to System on Chip Design” Springer, 2005.

END SEMESTER EXAMINATION QUESTION PAPER PATTERN
Max. Marks: 100 Exam Duration: 3 Hrs.
PART A: 10 Questions of 2 marks each – No choice 20 Marks
PART B: 2 Questions from each unit of internal choice; each carrying 16 marks 80 Marks