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No problem I will provide you Anna University, DPSD Subject exam paper so that it would be easy for you to check the exam questions. Here is the exam paper PART A - (10 X 2 = 20 Marks) 1. Represent the decimal numbers -200 & 200 using 2’s complement binary form. 2. Write the truth table of AND and XOR gates. 3. Draw the schematic of half adder logic. 4. Write the HDL descriptor of following circuit. 5. Determine the size & number of multiplexers required to implement the full adder. 6. Determine the no of address lines required for 512 bytes of memory and for 2kb memory. 7. Write state transition diagram of JK Flip-flop. 8. Draw the timing diagram showing the output of a 2 stage synchronous counter with respect to its clock signal. 9. Explain the next state characteristics of D and SR flip-flops. 10. Define static and dynamic hazards. ![]() ![]() For full information please check the file |
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