[prince karak]

Sathyabama Institute of Science and Technology BE ECE SECA3014 Electronic Test Engineering Syllabus

SATHYABAMA INSTITUTE OF SCIENCE AND TECHNOLOGY SCHOOL OF ELECTRICAL AND ELECTRONICS

SECA3014 ELECTRONIC TEST ENGINEERING
L T P Credits Total Marks
3 0 0 3 100

UNIT 1 INTRODUCTION TO PCB TESTING METHODS 9 Hrs.
Printed Circuit Boards(PCB) - Construction - Types of PCB - Multilayer - Surface Mount technology – PCB Manufacturing
process - PCB Inspection methods - Bare Board Testing - Optical and X-Ray Inspection - Electrical tests -Text fixtures - Bed
of nails fixtures - Cross talk test - Mock up test - In circuit test – Burn-in-test - Fault diagnostic methods. Electromagnetic
compatibility testing of electronic components, subassemblies, Measuring Instruments and systems.

UNIT 2 INTRODUCTION TO TESTING TOOLS AND INSTRUMENTS 9 Hrs.
Symptom Recognition - Bracketing Technique - Component failure Analysis - Fault types and causes in circuits - during
manufacturing - Manual trouble shooting technique - Tools and Instruments DMM - CRO - PCO - Logic probes-- Logic
pulsar - Logic Analyzer.

UNIT 3 INTRODUCTION TO AUTOMATED TESTING METHODS 9 Hrs.
ATE Techniques - CPU Emulator technique - ROM amd ROM Emulators - In circuit Comparator - In Circuit Functional test -
Trouble shooting digital gates - Testing Linear Integrated Circuits - Guarding Technique - VI trace Technique - Bus Cycle
Signature System - Board functional test methods - Boundary scan test basics.

UNIT 4 TEST VECTOR GENERATION AND FAULT SIMULATION 9 Hrs.
ATE System Components - Digital Pin Electronics - Drive data formats - Digital High way - Analog Highway – Test Vector
Generation - Creating test patterns - Fault Simulations.

UNIT 5 DESIGN FOR TESTABILITY 9 Hrs.
MDA test systems - Boundary scan test with I/O pin compatibility - Automatic optical inspection systems - Combinational
ATE Systems - Design for testability - Observability and Controllability - Testing Flow diagram - Stuck at fault model - Fault
simulation - Ad Hoc technique - Scan design technique - Basics of ATPG - BIST-Test pattern generation for built in self test -
Exhaustive pattern generation and deterministic testing - Output response Analysis - Transition count syndrome checking -
Signature Analysis - Circular BIST.
Max. 45 Hrs.

COURSE OUTCOMES
On completion of the course, student will be able to
CO1 - Identify various types of printed circuit boards and effectively use testing tools.
CO2 - Describe the working of automated test equipments.
CO3 - Identify faults in assembled PCBs using automated test equipments both at component level and board level.
CO4 - Design board fixtures to carry out customized board level testing.
CO5 - Develop test vectors and test patterns for fault identification in custom PCBs.
CO6 - Design and implement electronic systems with testability architectures.

TEXT / REFERENCE BOOKS
1. Michael L.Bushnell et al., “Essentials of Electronic testing for digital, memory and mixed signal VLSI circuit”,1st Edition,
Academic Press, 2002.
2. Randall L Geiger, Pillip E Allen, “VLSI design techniques for analog and digital circuits”, MGH, 1990.
3. Parag.K.lala, “Digital circuit Testing and Testability”, 1st Edition, Academic press, 2001.
4. Alfred L.Crouch, “Design for test for Digital ICs and Embedded core systems”, 2nd Edition, PHI, 1999.
5. Sabapathy S.R., “Test Engineering for electronic hardware”, Qmax publishers, 1st Edition, 2007.

END SEMESTER EXAMINATION QUESTION PAPER PATTERN
Max. Marks: 100 Exam Duration: 3 Hrs.
PART A: 10 Questions of 2 marks each – No choice 20 Marks
PART B: 2 Questions from each unit of internal choice; each carrying 16 marks 80 Marks