[prince karak]

Sathyabama Institute of Science and Technology M.Tech - VLSI SECA5102 Advanced Digital System Design using VHDL Syllabus

SATHYABAMA INSTITUTE OF SCIENCE AND TECHNOLOGY SCHOOL OF ELECTRICAL AND ELECTRONICS ENGINEERING

SECA5102
ADVANCED DIGITAL SYSTEM DESIGN
USING VHDL (For VLSI)
L T P Credits Total Marks
3 0 0 3 100

UNIT 1 SYNCHRONOUS SEQUENTIAL NETWORKS 9 Hrs.
Structure and Operation of Synchronous Sequential Networks; Analysis of Clocked Synchronous Sequential Networks
(CSSN); Modeling of CSSN Behavior; State Table Reduction; State Assignment; Design of CSSN – Realization using
Programmable Logic Devices; Algorithmic state Machines – ASM Charts, ASM Tables, Sate Assignments, ASM
Realizations.

UNIT 2 ASYNCHRONOUS SEQUENTIAL NETWORKS 9 Hrs.
Structure and Operation of Asynchronous Sequential Networks (Fundamental and Pulse Mode); Analysis of Asynchronous
Sequential Networks (ASN); Races in ASC; Primitive Flow Table; Flow Table Reduction; State Assignment; Transition
Table; Design of ASN; Static and Dynamic Hazards; Essential Hazards; Data Synchronizers; Mixed Operating Mode
Asynchronous Circuits.

UNIT 3 LOGIC DESIGN USING PROGRAMMABLE DEVICES 9 Hrs.
Sequential Circuit Design Using ROMs, PLAs, CPLDs and FPGAs; Introduction to Field Programmable Gate Arrays; Types
of FPGA; Xilinx FPGA – Architecture of Xilinx 3000, Xilinx 4000 families.

UNIT 4 INTRODUCTION TO VHDL 9 Hrs.
Introduction to VHDL; Modeling Styles; Data Objects, Data Types, Delay Models; Concurrent Statements; Sequential
Statements; Process Statements; Conditional & Selective Signal and Variable Assignments; Synthesis of Statements;
Functions; IEEE Standard Logic Library; Test Bench; Component Declaration; Instantiation; Configuration- Declaration &
Specification.

UNIT 5 LOGIC DESIGN USING VHDL 9 Hrs.
Modeling Using VHDL Processes – Flip flops, Registers, Counters, Combinational Logic, Sequential Machine; Synthesis of
VHDL code.
Max. 45 Hrs.

COURSE OUTCOMES
On completion of the course, student will be able to
CO1 - Clear insight on the state table reduction and state assignment, ASM chart and ASM Tables in the design of
synchronous sequential Networks.
CO2 - Critical Analysis on the Real Time Challenges in the design of Asynchronous sequential circuits.
CO3 - Explores the feasibility of sequential circuit design using PLA and PLD’s, Data types and Relay models.
CO4 - Understanding the process statements and conditions assigned statements.
CO5 - Logical modelling of combination and sequential logic circuits in VHDL.
CO6 - Construct and develop a VHDL for conventional mathematical operations.

TEXT / REFERENCE BOOKS
1. Donald G. Givone, "Digital principles and Design", Tata McGraw Hill,2002.
2. Stephen Brown and Zvonk Vranesic, "Fundamentals of Digital Logic with VHDL Design", Tata McGraw Hill,2002.
3. John M Yarbrough, "Digital Logic applications and Design", Thomson Learning,2001.
4. William I. Fletcher, "An Engineering Approach to Digital Design", Prentice Hall of India,1996.

END SEMESTER EXAMINATION QUESTION PAPER PATTERN
Max. Marks: 100 Exam Duration: 3 Hrs.
PART A: 5 Questions of 6 Marks each – No choice 30 Marks
PART B: 2 Questions from each unit of internal choice, each carrying 14 Marks 70 Marks